1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to high dielectric constant layers with improved dielectric characteristics provided by employing a nucleation method prior to formation of the high dielectric constant layer.
2. Description of the Related Art
The art of semiconductor fabrication is driven by the desire to continually shrink device sizes and improve component capabilities. These goals are often contradictory. While decreasing sizes of devices provides a more efficient layout, component features such as dielectric films or layers are pushed to their limit. Often, materials or processes used to form these dielectric films or layers become inadequate for future chip generations. Deposition processes and dielectric materials are usually reduced in size along with the shrinking device dimensions. This often requires the reduced size dielectric material to electrically isolate components with at least the same capacity as earlier generations.
In other cases, improved dielectric layers not only provide less thickness or layout area but may also improve performance. For example, capacitor dielectric layers for stacked capacitors for dynamic random access memories (DRAM) include a high dielectric constant layer between two electrodes. Improvements in the dielectric layer between the electrodes provide a more reliable device and increase capacitance.
Referring to FIG. 1, major elements of a semiconductor memory cell are illustratively shown. Stacked capacitors 10 are shown having a top electrode 16, a bottom electrode 18 and a capacitor dielectric layer 20 therebetween. Bottom electrode 18 is provided on a dielectric layer 19 and is connected to a plug 22 which extends down to a portion of active area 12. Active areas 12 form an access transistor for charging and discharging stack capacitor 10 in accordance with data on a bitline 24. Bitline 24 is coupled to a portion of active area 12 (source or drain of the access transistor) by a contact 23. When a gate conductor 28 is activated the access transistor conducts and charges or discharges stack capacitor 10. When the minimum feature size is reduced with each new generation of the memory design, stacked capacitor 12 loses area thereby reducing the capacitor's capabilities. Capacitor dielectric layer 20 may formed from a high dielectric constant material to increase capacitance. Barium strontium titanium oxide (BSTO) is typically employed.
BSTO may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD) or other processes. CVD is preferred to get high step coverage around the bottom electrode. In a one step CVD process, BSTO films are deposited at a constant temperature for a given time by controlling, primarily, the deposition pressure and BSTO composition. In a two step (or multi-step) deposition process, a first step is to deposit a continuous BSTO film at a lower temperature to obtain an amorphous film. A second step is employed to deposit another continuous BSTO film at a higher temperature to obtain a crystallized BSTO film. An anneal step is needed to crystallize the first layer of the amorphous BSTO film either before or after depositing the second BSTO film. Although BSTO provides a high dielectric constant layer between capacitor electrodes, it would be advantageous to increase the capabilities of the dielectric layer between the two capacitor electrodes to improve performance and reduce possible leakage.
Therefore, a need exists for a method for improving the dielectric characteristics of a deposited dielectric layer. A further need exists for a dielectric layer which has improved dielectric characteristic without cost to layout area and without increase to the thickness of the dielectric layer.